ESM Control Registers
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SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.30 ESM Status Register 7 (ESMSR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-40. ESM Status Register 7 (ESMSR7) [offset = 98h]
31 16
ESF[95:80]
R/W1CP-X/0
15 0
ESF[79:64]
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = value is unchanged
Table 16-32. ESM Status Register 7 (ESMSR7) Field Descriptions
Bit Field Value Description
95-64 ESF Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1 Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the
interrupt service routine will be called.
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