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PMM Registers
285
SPNU563A–March 2018
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Power Management Module (PMM)
Compare mismatch test:
A vector with all 1's is applied to the PSCON diagnostic compare block’s primary input port and the same
input is also applied to the secondary input port but with one bit flipped starting from bit position 0. The
unequal vectors should cause the PSCON diagnostic compare block to generate a compare mismatch at
bit position 0. In case a mismatch is not detected, a self-test error is indicated. This compare mismatch
test algorithm is repeated until every single bit position is verified on both PSCON signal ports.
5.3.7.3 Error-Forcing Mode
This mode is designed specifically to ensure that the error signal output from the PSCON compare block
is not stuck inactive. In this mode, a test pattern is applied to the PSCON related inputs of the compare
logic to force an error. The application can clear the flag for ESM group1 channel 38 once the error is
flagged. If the ESM group1 channel 38 flag does not get set, this indicates that the PSCON compare error
signal is stuck inactive and cannot be relied upon to detect a PSCON mismatch.
5.3.7.4 Self-Test Error-Forcing Mode
In this mode, an error is forced so that the self-test error output from the PSCON compare block is
activated. The application can clear the flag for ESM group1 channel 39 once the error is flagged. If the
ESM group1 channel 39 flag does not get set, this indicates that the PSCON compare block self-test error
signal is stuck inactive and there is no self-test mechanism available for the PSCON compare block.
5.3.7.5 PMM Operation During CPU Halt Debug Mode
No compare errors are generated when the CPU is halted in debug mode, regardless of the mode of the
diagnostic compare block. No status flags are updated in this mode. Normal operation of the compare
block is resumed once the CPU exits the debug mode.
5.4 PMM Registers
Table 5-1 lists the control registers in the PMM module. The registers support 8-, 16-, and 32-bit
accesses. The address offset is specified from the base address of FFFF 0000h. Any access to an
unimplemented location within the PMM register frame will generate a bus error that results in an Abort
exception.
Table 5-1. PMM Registers
Offset Acronym Register Description Section
00h LOGICPDPWRCTRL0 Logic Power Domain Control Register 0 Section 5.4.1
04h LOGICPDPWRCTRL1 Logic Power Domain Control Register 1 Section 5.4.2
20h PDCLKDIS Power Domain Clock Disable Register Section 5.4.3
24h PDCLKDISSET Power Domain Clock Disable Set Register Section 5.4.4
28h PDCLKDISCLR Power Domain Clock Disable Clear Register Section 5.4.5
40h LOGICPDPWRSTAT0 Logic Power Domain PD2 Power Status Register Section 5.4.6
44h LOGICPDPWRSTAT1 Logic Power Domain PD3 Power Status Register Section 5.4.7
48h LOGICPDPWRSTAT2 Logic Power Domain PD4 Power Status Register Section 5.4.8
4Ch LOGICPDPWRSTAT3 Logic Power Domain PD5 Power Status Register Section 5.4.9
50h LOGICPDPWRSTAT4 Logic Power Domain PD6 Power Status Register Section 5.4.10
A0h GLOBALCTRL1 Global Control Register 1 Section 5.4.11
A8h GLOBALSTAT Global Status Register Section 5.4.12
ACh PRCKEYREG PSCON Diagnostic Compare Key Register Section 5.4.13
B0h LPDDCSTAT1 LogicPD PSCON Diagnostic Compare Status Register 1 Section 5.4.14
B4h LPDDCSTAT2 LogicPD PSCON Diagnostic Compare Status Register 2 Section 5.4.15
C0h ISODIAGSTAT Isolation Diagnostic Status Register Section 5.4.16
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