Device Level Interrupt Management
www.ti.com
666
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Vectored Interrupt Manager (VIM) Module
19.3.2 Interrupt Handling at the CPU
The ARM CPU provides two vectors for interrupt requests—fast interrupt requests (FIQs) and normal
interrupt requests (IRQs). FIQs are higher priority than IRQs, and FIQ interrupts may interrupt IRQ
interrupts.
NOTE: The FIQ implemented in Cortex-R4F/R5F is Non-Maskable Fast Interrupts (NMFI). Once FIQ
is enabled (by clearing F bit in CPSR), it can NOT be disabled by setting F bit in CPSR. Only
a reset or an FIQ will be able to set the F bit in CPSR. By hardware, Non Maskable FIQ are
not reentrant.
After reset (power reset or warm reset), both FIQ and IRQ are disabled. The CPU may enable these
interrupt request channels individually within the CPSR (Current Program Status Register); CPSR bits 6
and 7 must be cleared to enable the FIQ (bit 6) and IRQ (bit 7) interrupt requests at the CPU. CPSR is
writable in privilege mode only. Example 19-2 shows how to enable the IRQ and FIQ through CPSR.
When the CPU receives an interrupt request, the CPSR mode field changes to either FIQ or IRQ mode.
When an IRQ interrupt is received, the CPU disables other IRQ interrupts by setting CPSR bit 7. When an
FIQ interrupt is received, the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and 7.
A write of 1 to CPSR bit 7 disables the IRQ from CPU. However, a write of 1 to CPSR bit 6 leaves it
unchanged. Example 19-2 also shows how to disable the IRQ through CPSR.
To Next Page
Loading...
Need help?
General
