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NMPU Registers
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SPNU563A–March 2018
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System Memory Protection Unit (NMPU)
11.4 NMPU Registers
The new memory protection unit (NMPU) registers listed in Table 11-3 are accessed through the system
module register space in the Cortex-R5F CPUs memory-map. All registers are 32-bit wide and are located
on a 32-bit boundary. Reads and writes to registers are supported in 8-, 16-, and 32-bit accesses. Refer to
the device specific datasheet for the base address of each instance of NMPU in the device.
NOTE: If a register is not implemented, corresponding address location behaves like a reserved
location, that is, reads return 0 and writes have no effect. User mode writes to NMPU
registers are ignored. No error response is given for such an access. Writes to registers
other than MPUERRSTAT register are ignored, when NMPU registers are locked (LOCK =
5h in MPULOCK register). No error response is given for such an access.
Table 11-3. NMPU Registers
Offset Acronym Register Description Section
00h MPUREV MPU Revision ID Register Section 11.4.1
04h MPULOCK MPU Lock Register Section 11.4.2
08h MPUDIAGCTRL MPU Diagnostics Control Register Section 11.4.3
0Ch MPUDIAGADDR MPU Diagnostic Address Register Section 11.4.4
10h MPUERRSTAT MPU Error Status Register Section 11.4.5
14h MPUERRADDR MPU Error Address Register Section 11.4.6
20h MPUCTRL1 MPU Control Register 1 Section 11.4.7
24h MPUCTRL2 MPU Control Register 2 Section 11.4.8
2Ch MPUTYPE MPU Type Register Section 11.4.9
30h MPUREGBASE MPU Region Base Address Register Section 11.4.10
34h MPUREGSENA MPU Region Size and Enable Register Section 11.4.11
38h MPUREGACR MPU Region Access Control Register Section 11.4.12
3Ch MPUREGNUM MPU Region Number Register Section 11.4.13
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