www.ti.com
Control Registers
1541
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.5 SPI Flag Register (SPIFLG)
Software must check all flag bits when reading this register.
Figure 28-36. SPI Flag Register (SPIFLG) [offset = 10h]
31 25 24 23 16
Reserved BUFINIT
ACTIVE
Reserved
R-0 R-0 R-0
15 10 9 8
Reserved TXINTFLG RXINTFLG
R-0 R-0 R/W1C-0
7 6 5 4 3 2 1 0
Reserved RXOVRNINT
FLG
Reserved BITERR
FLG
DESYNC
FLG
PARERR
FLG
TIMEOUT
FLG
DLENERR
FLG
R-0 R/W1C-0 R-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 28-13. SPI Flag Register (SPIFLG) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reads return 0. Writes have no effect.
24 BUFINITACTIVE Indicates the status of multi-buffer initialization process. Software can poll for this bit to
determine if it can proceed with the register configuration of multi-buffer mode registers or buffer
handling.
Note: If the SPIFLG register is read while the multi-buffer RAM is being initialized, the
BUF INIT ACTIVE bit will be read as 1. If SPIFLG is read after the internal automatic
buffer initialization is complete, this bit will be read as 0. This bit will show a value of 1
as long as the nRESET bit is 0, but does not really indicate that buffer initialization is
underway. Buffer initialization starts only when the nRESET bit is set to 1.
0 Multi-buffer RAM initialization is complete.
1 Multi-buffer RAM is still being initialized. Do not attempt to write to either multi-buffer RAM or
any multi-buffer mode registers.
23-10 Reserved 0 Reads return 0. Writes have no effect.
9 TXINTFLG Transmitter-empty interrupt flag. Serves as an interrupt flag indicating that the transmit buffer
(TXBUF) is empty and a new word can be written to it. This flag is set when a word is copied to
the shift register either directly from SPIDAT0/SPIDAT1 or from the TXBUF register. This bit is
cleared by one of following methods:
• Writing a new data to either SPIDAT0 or SPIDAT1
• Writing a 0 to SPIEN (SPIGCR1[24])
0 Transmit buffer is now full. No interrupt pending for transmitter empty.
1 Transmit buffer is empty. An interrupt is pending to fill the transmitter.
To Next Page
Loading...
Need help?
General
