Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-13. SPI Flag Register (SPIFLG) Field Descriptions (continued)
Bit Field Value Description
8 RXINTFLG Receiver-full interrupt flag. This flag is set when a word is received and copied into the buffer
register (SPIBUF). If RXINTEN is enabled, an interrupt is also generated. This bit is cleared
under the following methods:
• Reading the SPIBUF register
• Reading TGINTVECT0 or TGINTVECT1 register when there is a receive buffer full interrupt
• Writing a 1 to this bit
• Writing a 0 to SPIEN (SPIGCR1[24])
• System reset
During emulation mode, however, a read to the emulation register (SPIEMU) does not clear this
flag bit.
0 No new received data pending. Receive buffer is empty.
1 A newly received data is ready to be read. Receive buffer is full.
Note: Clearing RXINTFLG bit by writing a 1 before reading the SPIBUF sets the RXEMPTY
bit of the SPIBUF register too. In this way, one can ignore a received word. However, if
the internal RXBUF is already full, the data from RXBUF will be copied to SPIBUF and the
RXEMPTY bit will be cleared again. The SPIBUF contents should be read first if this
situation needs to be avoided.
7 Reserved 0 Reads return 0. Writes have no effect.
6 RXOVRNINTFLG Receiver overrun flag. The SPI hardware sets this bit when a receive operation completes
before the previous character has been read from the receive buffer. The bit indicates that the
last received character has been overwritten and therefore lost. The SPI will generate an
interrupt request if this bit is set and the RXOVRN INTEN bit (SPIINT0.6) is set high. This bit is
cleared under the following conditions in compatibility mode of MibSPI:
• Reading TGINTVECT0 or TGINTVECT1 register when there is a receive-buffer-overrun
interrupt
• Writing a 1 to RXOVRNINTFLG in the SPI Flag Register (SPIFLG) itself
• Writing a 0 to SPIEN
• Reading the data field of the SPIBUF register
Note: Reading the SPIBUF register does not clear this RXOVRNINTFLG bit. If an RXOVRN
interrupt is detected, then the SPIBUF may need to be read twice to get to the overrun
buffer. This is due to the fact that the overrun will always occur to the internal RXBUF.
Each read to the SPIBUF will result in RXBUF contents (if it is full) getting copied to
SPIBUF.
Note: There is a special condition under which the RXOVRNINTFLG flag gets set. If both
SPIBUF and RXBUF are already full and while another reception is underway, if any
errors (TIMEOUT, BITERR, and DLEN_ERR) occur, then RXOVR in RXBUF and
RXOVRNINTFLG in SPIFLG registers will be set to indicate that the status flags are
getting overwritten by the new transfer. This overrun should be treated like a receive
overrun.
In multi-buffer mode of MibSPI, this bit is cleared under the following conditions:
• Reading the RXOVRN_BUF_ADDR register
• Writing a 1 to RXOVRNINTFLG in the SPI Flag Register (SPIFLG) itself
In multi-buffer mode, if RXOVRNINTFLG is set, then the address of the buffer which
experienced the overrun is available in RXOVRN_BUF_ADDR.
0 Overrun condition did not occur.
1 Overrun condition has occurred.
5 Reserved 0 Reads return 0. Writes have no effect.
4 BITERRFLG Mismatch of internal transmit data and transmitted data. This flag can be cleared by one of the
following methods:
• Write a 1 to this bit.
• Clear the SPIEN bit to 0.
0 No bit error occurred.
1 A bit error occurred. The SPI samples the signal of the transmit pin (master: SIMO, slave:
SOMI) at the receive point (half clock cycle after transmit point). If the sampled value differs
from the transmitted value a bit error is detected and the flag BITERRFLG is set. If BITERRENA
is set an interrupt is asserted. Possible reasons for a bit error can be an excessively high bit
rate, capacitive load, or another master/slave trying to transmit at the same time.
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