STC Control Registers
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.8.2 STC Global Control Register 1 (STCGCR1)
This register is described in Figure 10-9 and Table 10-10.
NOTE: On a power-on reset or system reset, this register resets to its default values. Also, this
register automatically resets to its default values at the completion of a self-test run.
The SEG0_CORE_SEL bits must be written first before the STC_ENA bits are written, in
order for the STC to properly initiate the selected core for self-test.
Figure 10-9. STC Global Control Register 1 (STCGCR1) [offset = 04h]
31 16
Reserved
R-0
15 12 11 8 7 4 3 0
Reserved SEG0_CORE_SEL Reserved STC_ENA
R-0 R/WP-0 R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset
Table 10-10. STC Global Control Register 1 (STCGCR1) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Reads return 0. Writes have no effect.
11-8 SEG0_CORE_SEL Selects cores in Segment 0 for self-test. These bits can be programmed only when
SEG0_CORE_SEL is 0000. Once the field is written it ignores all further writes until the
self-test sequence completes. This is to maintain coherency for self-test runs.
5h Select only Core1 for self-test.
Ah Select only Core2 for self-test.
All other values Select both cores for self-test in parallel.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 STC_ENA Self-test run enable key.
Ah Self-test run is enabled.
All other values Self-test run is disabled.
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