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System and Peripheral Control Registers
151
SPNU563A–March 2018
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Architecture
2.5 System and Peripheral Control Registers
The following sections describe the system and peripheral control registers of the TMS570LC43x
microcontroller.
2.5.1 Primary System Control Registers (SYS)
This section describes the SYSTEM registers. These registers are divided into two separate frames. The
start address of the primary system module frame is FFFF FF00h. The start address of the secondary
system module frame is FFFF E100h. The registers support 8-, 16-, and 32-bit writes. The offset is relative
to the system module frame start address.
Table 2-18 contains a list of the primary system control registers.
Table 2-18. Primary System Control Registers
Offset Acronym Register Description Section
00h SYSPC1 SYS Pin Control Register 1 Section 2.5.1.1
04h SYSPC2 SYS Pin Control Register 2 Section 2.5.1.2
08h SYSPC3 SYS Pin Control Register 3 Section 2.5.1.3
0Ch SYSPC4 SYS Pin Control Register 4 Section 2.5.1.4
10h SYSPC5 SYS Pin Control Register 5 Section 2.5.1.5
14h SYSPC6 SYS Pin Control Register 6 Section 2.5.1.6
18h SYSPC7 SYS Pin Control Register 7 Section 2.5.1.7
1Ch SYSPC8 SYS Pin Control Register 8 Section 2.5.1.8
20h SYSPC9 SYS Pin Control Register 9 Section 2.5.1.9
30h CSDIS Clock Source Disable Register Section 2.5.1.10
34h CSDISSET Clock Source Disable Set Register Section 2.5.1.11
38h CSDISCLR Clock Source Disable Clear Register Section 2.5.1.12
3Ch CDDIS Clock Domain Disable Register Section 2.5.1.13
40h CDDISSET Clock Domain Disable Set Register Section 2.5.1.14
44h CDDISCLR Clock Domain Disable Clear Register Section 2.5.1.15
48h GHVSRC GCLK1, HCLK, VCLK, and VCLK2 Source Register Section 2.5.1.16
4Ch VCLKASRC Peripheral Asynchronous Clock Source Register Section 2.5.1.17
50h RCLKSRC RTI Clock Source Register Section 2.5.1.18
54h CSVSTAT Clock Source Valid Status Register Section 2.5.1.19
58h MSTGCR Memory Self-Test Global Control Register Section 2.5.1.20
5Ch MINITGCR Memory Hardware Initialization Global Control Register Section 2.5.1.21
60h MSINENA Memory Self-Test/Initialization Enable Register Section 2.5.1.22
68h MSTCGSTAT MSTC Global Status Register Section 2.5.1.23
6Ch MINISTAT Memory Hardware Initialization Status Register Section 2.5.1.24
70h PLLCTL1 PLL Control Register 1 Section 2.5.1.25
74h PLLCTL2 PLL Control Register 2 Section 2.5.1.26
78h SYSPC10 SYS Pin Control Register 10 Section 2.5.1.27
7Ch DIEIDL Die Identification Register, Lower Word Section 2.5.1.28
80h DIEIDH Die Identification Register, Upper Word Section 2.5.1.29
88h LPOMONCTL LPO/CLock Monitor Control Register Section 2.5.1.31
8Ch CLKTEST Clock Test Register Section 2.5.1.31
90h DFTCTRLREG DFT Control Register Section 2.5.1.32
94h DFTCTRLREG2 DFT Control Register 2 Section 2.5.1.33
A0h GPREG1 General Purpose Register Section 2.5.1.34
B0h SSIR1 System Software Interrupt Request 1 Register Section 2.5.1.35
B4h SSIR2 System Software Interrupt Request 2 Register Section 2.5.1.36
B8h SSIR3 System Software Interrupt Request 3 Register Section 2.5.1.37
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