System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
Table 2-18. Primary System Control Registers (continued)
Offset Acronym Register Description Section
BCh SSIR4 System Software Interrupt Request 4 Register Section 2.5.1.38
C0h RAMGCR RAM Control Register Section 2.5.1.39
C4h BMMCR1 Bus Matrix Module Control Register 1 Section 2.5.1.40
CCh CPURSTCR CPU Reset Control Register Section 2.5.1.41
D0h CLKCNTL Clock Control Register Section 2.5.1.42
D4h ECPCNTL ECP Control Register Section 2.5.1.43
DCh DEVCR1 DEV Parity Control Register 1 Section 2.5.1.44
E0h SYSECR System Exception Control Register Section 2.5.1.45
E4h SYSESR System Exception Status Register Section 2.5.1.46
E8h SYSTASR System Test Abort Status Register Section 2.5.1.47
ECh GLBSTAT Global Status Register Section 2.5.1.48
F0h DEVID Device Identification Register Section 2.5.1.49
F4h SSIVEC Software Interrupt Vector Register Section 2.5.1.50
F8h SSIF System Software Interrupt Flag Register Section 2.5.1.51
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