System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.1.51 System Software Interrupt Flag Register (SSIF)
The SSIF register, shown in Figure 2-58 and described in Table 2-70, contains software interrupt flag
status information.
Figure 2-58. System Software Interrupt Flag Register (SSIF) (offset = F8h)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 4 3 2 1 0
Reserved SSI_FLAG4 SSI_FLAG3 SSI_FLAG2 SSI_FLAG1
R-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 2-70. System Software Interrupt Flag Register (SSIF) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 SSI_FLAG[4-1] System software interrupt flag[4-1]. This flag is set when the correct SSKEY is written to the
SSIR register[4-1].
Note: A read from the SSIVEC register clears the corresponding SSI_FLAG[4-1] bit in the
SSIF, corresponding to the source vector of the system software interrupt.
0 Read: No IRQ/FIQ interrupt was generated since the bit was last cleared.
Write: The bit is unchanged.
1 Read: An IRQ/FIQ interrupt was generated.
Write: The bit is cleared to 0.
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