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Self-Test Controller Diagnostics
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.10 Self-Test Controller Diagnostics
This section provides the recommended flow for the self-test controller diagnostics. This test is
recommended to be done at the application startup only, not with individual interval runs during the
application.
Step 1: Configure the interval count to 1 in STCGCR0 register.
Segment 0
Step 2: Enable the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register and kick off the
self-test by enabling the first interval of segment 0. On the completion of self-test, TEST_FAIL bit will be
set in the STCGSTAT register. Check if the FSEGID bits in the STCFSTAT register are set to 00.
Depending on the segment 0 configuration (parallel or individual cores), the CORE1_FAIL or
CORE2_FAIL bits would be set.
Step 3: Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register.
Then restart the self-test by programming bit 0 of the STCGCR0 register to 1. On the completion of the
test, the TEST_FAIL bit will be cleared in the STCGSTAT register.
Segment 1 (for STC1 only)
Step 4: Configure the SEGID_PLOAD bits in STCSEGPLR register to select the first interval of segment 1.
Configure RS_CNT bit in STCGCR0 register to 1. This will start the self-test from the first interval of the
selected segment. On the completion of self-test, TEST_FAIL bit will be set in the STCGSTAT register.
Check if the FSEGID bits in the STCFSTAT register are set to 01.
Step 5: Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register.
Then restart the self-test by programming bit 0 of the STCGCR register to 1. On the completion of the test,
the TEST_FAIL bit will be cleared in the STCGSTAT register.
After the diagnostics, the application can continue with the self-test as described in Section 10.4.
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