HTU Control Registers
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SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.4.21 Watch Point Register (HTU WPR)
This register defines the main memory address of the watch point.
Figure 24-34. Watch Point Register (HTU WPR) [offset = 58h]
31 16
WP
R/WS-0
15 0
WP
R/WS-0
LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset
Table 24-34. Watch Point Register (HTU WPR) Field Descriptions
Bit Field Description
31-0 WP Watch Point Register
A 32-bit address can be programmed into this register as a watch point. The WPR register is used along with
the Watch Mask Register ( WMR). When the main memory address is equal to the unique address defined by
WPR, or lies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution is stopped.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL and
WMR registers are reset by the test reset (nTRST) but not by the normal device reset.
24.4.22 Watch Mask Register (HTU WMR)
This register defines a mask of the main memory address of the watch point. It can be used to define a
memory range in conjunction with the WPR register.
Figure 24-35. Watch Mask Register (HTU WMR) [offset = 5Ch]
31 16
WM
R/WS-0
15 0
WM
R/WS-0
LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset
Table 24-35. Watch Mask Register (HTU WMR) Field Descriptions
Bit Field Description
31-0 WM Watch Mask Register
Setting a bit in the WMR register to 1 has the effect of masking the corresponding bit in of the main memory
address, so that this bit is ignored for the address comparison.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL and
WPR registers are reset by the test reset (nTRST) but not by the normal device reset.
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