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CPU Interconnect Subsystem
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SPNU563A–March 2018
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Interconnect
4.3.1.4 Accessing Cache Memories
Both the instruction and data caches of theCPU are memory mapped in the device and can be accessed
via the AXI-S slave port. Only the CPU core has point to point connection to the AXI-S slave port.
4.3.2 ECC Generation and Evaluation
CPU core contains the built-in ECC generation and evaluation logic for its AXI interface. Therefore, CPU
will generate the ECC checksum along with its write data. The write data and the corresponding ECC
checksum are transported by the interconnect to the selected slave such as L2 SRAM. When CPU core
performs a read from a slave, the slave returns the data and the corresponding ECC checksum. Upon
receiving the data and the ECC checksum, the CPU will evaluate the integrity of the data by performing
the ECC check. ECC errors detected on the CPU's AXI interface are exported by the CPU to its event bus
output. The error signals if enabled and the corresponding error addresses are first routed to the Error
Profiling Controller (EPC) module. EPC is used to record different single bit error addresses in a Content
Addressable Memory (CAM). The main purpose of the EPC module is to enable the system to tolerate a
certain amount of ECC correctable errors on the same address repeated in the memory system with
minimal runtime overhead. If an ECC error is generated on a repeating address, the EPC will not raise an
error to ESM module. This tolerance avoids the application to handle the same error when the code is in a
repeating loop. See EPC chapter for more information.
DMA PortA and PS_SCR_M masters do not have built-in ECC generation and evaluation logic. Therefore,
the CPU Interconnect Subsystem contain a standalone ECC generation and evaluation logic for each
DMA PortA and PS_SCR_M master. Write transactions initiated by the DMA PortA and PS_SCR_M
masters are first treated by the ECC block to generate the ECC checksum before transporting to the final
destination. For read transactions, the data and ECC checksum returned by the slaves will pass through
the ECC block for data integrity evaluation.
ECC errors detected are also routed to the Error Profiling Controller (EPC) module. In order for the
standalone ECC block to assert the error signals to the EPC, the error enable key must be first set in the
IP1ECCERREN register of the SYS2 module.
NOTE: To enable error signal assertion to the ESM for ECC errors detected for DMA, the application
must write 0xA to the IP1_ECC_KEY bits. To enable error signal assertion to the ESM for
ECC errors detected for PS_SCR_M, the application must write 0xA to the IP2_ECC_KEY
bits.
4.3.3 Safety Diagnostic Checker
For each master and slave interface in the CPU Interconnect Subsystem, there is a runtime Safety
Diagnostic Checker. The hardware checker continuously watches transactions flowing through the
interconnect and ensuring they are non corrupted at all time. If a mismatch is detected between an
ongoing transaction and the expected transaction flow then an error is asserted to the ESM Group 1.
Types of errors are recorded in the SDC MMR registers. See Section 4.4 for all the registers. Once an
error is detected and the error type is logged, the application will clear the runtime diagnostic errors by
writing an 0xA key to the GLOBAL_ERROR_CLR bits of the SCMCNTRL register in the SCR Control
Module (SCM). See the SCM Chapter for more information.
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