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Overview
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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
26.1 Overview
The FlexRay module performs communication according to the FlexRay protocol specification v2.1 Rev.
A. The sample clock bit rate can be programmed to values up to 10 Mbit/s. Additional bus driver (BD)
hardware is required for connection to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the message
handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay
Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as
providing message status information.
The register set of the FlexRay module can be accessed directly by the CPU via the VBUS interface.
These registers are used to control, configure and monitor the FlexRay channel protocol controllers,
message handler, global time unit, system universal control, frame and symbol processing, network
management, interrupt control, and to access the message RAM via the input / output buffer.
26.1.1 Feature List
• Conformance with FlexRay protocol specification v2.1 Rev. A
• Data rates of up to 10 Mbit/s on each channel
• Up to 128 message buffers
• 8 Kbyte of message RAM for storage of, for example, 128 message buffers with maximum of 48-byte
data section or up to 30 message buffers with 254-byte data section
• Configuration of message buffers with different payload lengths
• One configurable receive FIFO
• Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive
FIFO
• CPU access to message buffers via input and output buffer
• Specialized DMA like FlexRay Transfer Unit (FTU) for automatic data transfer between data memory
and message buffers without CPU interaction
• Filtering for slot counter, cycle counter, and channel
• Maskable module interrupts
• Supports Network Management
26.1.2 FlexRay Module Block Diagram
The TI FlexRay module, Figure 26-1, contains the following blocks:
• Peripheral Interface (VBUS IF)
Interface to the Peripheral Bus of the TMS570 microcontroller architecture. The FlexRay module can
either act as a VBUS master or VBUS slave.
• FlexRay Transfer Unit (FTU)
The internal intelligent state-machine (Transfer Unit State Machine) is able to transfer data between
the input buffer (IBF) and output buffer (OBF) of the communication controller and the system memory
without CPU interaction.
NOTE: Since the FlexRay module is accessed through the FTU, the FTU must be powered up by
the corresponding bit in the Peripheral Power Down Registers of the System Module before
accessing any FlexRay module register. For details, refer to the Architecture chapter and the
device-specific data manual.
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