Control Registers
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SPNU563A–March 2018
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CPU Compare Module for Cortex-R5F (CCM-R5F)
13.3.5 CCM-R5F Status Register 3 (CCMSR3)
Figure 13-7. CCM-R5F Status Register 3 (CCMSR3) (Offset = 10h)
31 17 16
Reserved CPME3
R-0 R/W1CP-0
15 9 8 7 2 1 0
Reserved STC3 Reserved STET3 STE3
R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 13-12. CCM-R5F Status Register 3 (CCMSR3) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reads return 0. Writes have no effect.
16 CMPE3 Compare Error for Checker CPU Inactivity Monitor.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: CPU signals are identical.
Write: Leaves the bit unchanged.
1 Read: CPU signal compare mismatch.
Write: Clears the bit.
15-9 Reserved Reads return 0. Writes have no effect.
8 STC3 Self-test Complete for Checker CPU Inactivity Monitor.
Note: This bit is always 0 when not in self-test mode. Once set, switching from self-test mode to
other modes will clear this bit.
Read/Write in User and Privileged mode.
0 Read: Self-test on-going if self-test mode is entered.
Write: Writes have no effect.
1 Read: Self-test is complete.
Write: Writes have no effect.
7-2 Reserved Reads return 0. Writes have no effect.
1 STET3 Self-test Error Type for Checker CPU Inactivity Monitor.
Read/Write in User and Privileged mode.
0 Read: Self-test failed during Compare Match Test if STE3 = 1.
Write: Writes have no effect.
1 Read: Self-test failed during Compare Mismatch Test if STE3 = 1.
Write: Writes have no effect.
0 STE3 Self-test Error for Checker CPU Inactivity Monitor.
Note: This bit gets updated when the self-test is complete or an error is detected.
Read/Write in User and Privileged mode.
0 Read: Self-test passed.
Write: Writes have no effect.
1 Read: Self-test failed.
Write: Writes have no effect.
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