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Module Operation
1269
SPNU563A–March 2018
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FlexRay Module
26.2.13.2.1 Host Handling of Uncorrectable ECC Multi-bit Errors
Uncorrectable errors caused by transient bit flips can be fixed by:
Self-healing
Uncorrectable errors located in:
• Input Buffer RAM 1,2
• Output Buffer RAM 1,2
• Data Section of Message RAM
• Transient Buffer RAM A
• Transient Buffer RAM B
• Transfer Configuration RAM (TCR)
are overwritten with the next write access to the disturbed bit(s) caused by host access or by FlexRay
communication.
CLEAR_RAMS Command
When called in DEFAULT_CONFIG or CONFIG state POC command CLEAR_RAMS initializes all
module-internal RAMs to 0 and the ECC bits are initialized accordingly, depending what mode is enabled.
Temporary Unlocking of Header Section
An uncorrectable error in the header section of a locked message buffer can be fixed by a transfer from
the input buffer to the locked buffer header section. For this transfer, the write-access to the IBCR
(specifying the message buffer number) must be immediately preceded by the unlock sequence normally
used to leave CONFIG state. For that single transfer the corresponding message buffer header is
unlocked, regardless whether it belongs to the FIFO or whether its locking is controlled by MRC.SEC(1-0),
and will be updated with new data.
NOTE: In case the previous methods do not work, it is recommended to execute the PBIST test at
device level to confirm a hard error in the module internal RAMs.
26.2.14 Interrupts
This section describes the transfer unit interrupts and the communication controller interrupts.
26.2.14.1 Transfer Unit Interrupts
26.2.14.1.1 Interrupt Structure
For transfer interrupts, one enable bit is provided for each bit in the transfer occurred status registers.
Maskable error interrupts are possible for all error conditions except ECC multi-bit error and memory
protection error.
The ECC multi-bit error and the memory protection error have separate non-maskable lines. Both turn off
the Transfer Unit after finishing the current word access cycle.
The single-bit error interrupt is maskable. On single-bit error, if single-bit error correction is turned off, the
Transfer Unit is turned off after finishing the current word access cycle.
Figure 26-30 shows the interrupt structure of the FlexRay Transfer Unit.
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