www.ti.com
PBIST Flow
409
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Programmable Built-In Self-Test (PBIST) Module
9.3.1 PBIST Sequence
Before starting the PBIST sequence, you should ensure that both the instruction cache and data cache
are disabled. By default, PBIST will test all on-chip SRAMs including both the instruction and data cache
memories. After reset, cache is disabled by default. If cache has been enabled, use the following code
example to disable the cache.
MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12 ; instruction cache disable
BIC R1, R1, #0x1 <<2 ; data cache disable
DSB
MCR p15, #0, R1, c1, c0, #0 ; disabled cache RAMs ISB
1. Configure the device clock sources and domains so that they are running at their target frequencies.
2. Program the GCLK1 to PBIST ROM clock ratio by configuring the ROM_DIV field (bits 9:8) of the
MSTGCR register of the system module. This device supports a max PBIST ROM clock frequency of
82.5MHz.
3. Enable PBIST Controller by setting bit 1 of MSIENA register in system module.
4. Enable the PBIST self-test by writing a value of 0x0A to bits 3:0 of the MSTGCR in the system module.
5. Wait for N VBUS clock cycles based on the HCLK to PBIST ROM clock ratio:
N = 16 when GCLK1:PBIST ROM clock is 1:1
N = 32 when GCLK1:PBIST ROM clock is 1:2
N = 64 when GCLK1:PBIST ROM clock is 1:4
N = 64 when GCLK1:PBIST ROM clock is 1:8
6. Write 1h to PACT register to enable the PBIST internal clocks.
7. Program the ALGO register to decide which algorithm from the instruction ROM must be selected (the
default value of ALGO register is all 1’s, meaning all algorithms are selected). Similarly, program the
RINFOL and RINFOU registers to indicate whether a particular RAM group in the instruction ROM
would get executed or not.
NOTE: In case of RAM Override (Override Register (OVER) = 00), the user should make sure that
only the algorithms that run on similar RAMs are selected. If a single port algorithm is
selected in ROM Algorithm Mask Register (ALGO), the RAM Info Mask Lower Register
(RINFOL) and RAM Info Mask Upper Register (RINFOU) must select only the single port
RAM’s. The same applies for two port RAM’s. Check Table 2-5 for information on the
memory types.
8. Program OVER = 1h to run PBIST self-test without RAM override. Program OVER = 0 to run PBIST
self-test with RAM Override.
9. Write a value of 3h to the ROM mask register should the microcode for the Algorithms as well as the
RAM groups loaded from the on-chip PBIST ROM.
10. Write DLR (Data Logger register) with 14h to configure the PBIST run in ROM mode and to enable the
configuration access. This starts the memory self-tests.
11. Wait for the PBIST self-test done by polling MSTDONE bit of MSTCGSTAT register in System
Module.
12. Once self-test is completed, check the Fail Status register FSRF0.
In case there is a failure (FSRF0 = 1h):
a. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
b. Read FSRC0 and FSRC1 registers that contain the failure count.
c. Read FSRA0 and FSRA1 registers that contain the address of first failure.
d. Read FSRDL0 and FSRDL1 registers that contain the failure data.
e. Write a value of 2h to the STR register to resume the test.
In case there is no failure (FSRF0 = 0), the memory self-test is completed.
a. Disable the PBIST internal clocks by writing a 0 to the PACT register.
b. Disable the PBIST self-test by writing a value of 5h to bits 3:0 of the MSTGCR in the system
module.
To Next Page
Loading...
Need help?
General
