PBIST Flow
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SPNU563A–March 2018
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Programmable Built-In Self-Test (PBIST) Module
13. Repeat steps 2 through 9 for subsequent runs with different RAM group and algorithm configurations.
14. After required Memory tests are completed, Resume or Start the Normal Application software.
NOTE: The contents of the selected memory before the test will be completely lost. User software
must take care of data backup if required. Typically the PBIST tests are carried out at the
beginning of Application software.
NOTE: Memory test fail information is reported in terms of RGS:RDS and not RAM GROUP. Check
Table 2-5 for information on the RGS:RDS information applicable to each memory being
tested.
If cache memory is selected to be part of the PBIST test then the contents will become incoherent with
respect to the level 2 memory after the PBIST test. The cache will need to be invalidated before cache
can be enabled for use by the CPU. In addition, if you are using ECC error checking scheme in the cache,
you must enable this by programming the CEC bits in the Auxiliary Control Register before invalidating the
cache, to ensure that the correct error code bits are calculated when the cache is invalidated. For more
information on the CEC bits in the Auxiliary Control Register, refer to the ARM
®
Cortex
®
-R5F Technical
Reference Manual.
Use the following example code to invalidate cache and enable cache.
MRC p15, #0, R1, c1, c0, #1 ; Read auxiliary control register
BIC R1, R1, #0x1, <<5 ; bit is default set to disable ECC. Clearing bit 5
MCR p15, #0, R1, c1, c0, #1 ; enable ECC, generate abort on ECC errors, enable
; hardware recovery
MRC p15, #0, R1, c1, c0, #0 ; Read system control register configuration data
ORR R1, R1, #0x1 <<12 ; instruction cache enable
ORR R1, R1, #0x1 <<2 ; data cache enable
DSB
MCR p15, #0, R0, c15, c5, #0 ; invalidate entire data cache
MCR p15, #0, R0, c7, c5, #0 ; invalidate entire instruction cache
MCR p15, #0, R1, c1, c0, #0 ; enable cache RAM
ISB ; You must issue an ISB instruction to flush the pipeline.
; This ensures that all subsequent instruction fetches
; see the effect of enabling the instruction cache
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