PMM Registers
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SPNU563A–March 2018
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Power Management Module (PMM)
5.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 5-7. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) (offset = 28h)
31 8
Reserved
R-0
7 5 4 3 2 1 0
Reserved PDCLK_DISCLR[4] PDCLK_DISCLR[3] PDCLK_DISCLR[2] PDCLK_DISCLR[1] PDCLK_DISCLR[0]
R-0 R/WP-n R/WP-n R/WP-n R/WP-n R/WP-n
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 5-6. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)
Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reads return 0. Writes have no effect.
4 PDCLK_DISCLR[4] Read in User and Privileged Mode returns the current value of PDCLK_DIS[4]. Write in Privileged
Mode only.
0 No effect to state of clocks to power domain PD6.
1 Enable clocks to logic power domain PD6.
3 PDCLK_DISCLR[3] Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. Write in Privileged
Mode only.
0 No effect to state of clocks to power domain PD5.
1 Enable clocks to logic power domain PD5.
2 PDCLK_DISCLR[2] Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. Write in Privileged
Mode only.
0 No effect to state of clocks to power domain PD4.
1 Enable clocks to logic power domain PD4.
1 PDCLK_DISCLR[1] Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. Write in Privileged
Mode only.
0 No effect to state of clocks to power domain PD3.
1 Enable clocks to logic power domain PD3.
0 PDCLK_DISCLR[0] Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged
Mode only.
0 No effect to state of clocks to power domain PD2.
1 Enable clocks to logic power domain PD2.
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