VIM Control Registers
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SPNU563A–March 2018
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Vectored Interrupt Manager (VIM) Module
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])
The interrupt register enable selectively enables individual request channels. Figure 19-27, Figure 19-28,
Figure 19-29, Figure 19-30 and Table 19-16 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.
Figure 19-27. Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h]
31 16
REQENASET0[31:16]
R/WP-0
15 2 1 0
REQENASET0[15:2] Reserved
R/WP-0 R-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 19-28. Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h]
31 0
REQENASET1[63:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-29. Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h]
31 0
REQENASET2[95:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-30. Interrupt Enable Set Register 3 (REQENASET3) [offset = 3Ch]
31 0
REQENASET3[127:96]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 19-16. Interrupt Enable Set Registers (REQENASET) Field Descriptions
Bit Field Value Description
127-2 REQENASETx[n] Request enable set bits. This vector determines whether the interrupt request channel is
enabled. Bit REQENASETx[127:2] corresponds to request channel[127:2].
0 Read: Interrupt request channel is disabled.
Write: No effect.
1 Read or Write: The interrupt request channel is enabled.
1-0 Reserved 3h Read only. Writes have no effect.
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