Texas Instruments TMS570LC4357

VIM Control Registers www.ti.com
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SPNU563A–March 2018
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Vectored Interrupt Manager (VIM) Module
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])
The wake-up enable registers selectively enables individual wake-up interrupt request lines. Figure 19-35,
Figure 19-36, Figure 19-37, Figure 19-38 and Table 19-18 describe these registers.
Figure 19-35. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h]
31 0
WAKEENASET0[31:0]
R/WP-FFFF FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-36. Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h]
31 0
WAKEENASET1[63:32]
R/WP-FFFF FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-37. Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h]
31 0
WAKEENASET2[95:64]
R/WP-FFFF FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-38. Wake-Up Enable Set Register 3 (WAKEENASET3) [offset = 5Ch]
31 0
WAKEENASET3[127:96]
R/WP-FFFF FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 19-18. Wake-Up Enable Set Registers (WAKEENASET) Field Descriptions
Bit Field Value Description
127-0 WAKEENASETx[n] Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled.
Bit WAKEENASETx[127:0] corresponds to interrupt request channel[127:0].
0 Read: Interrupt request channel is disabled.
Write: No effect.
1 Read or Write:The interrupt request channel is enabled.