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ADC Registers
943
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) is shown in Figure 22-91 and
described in Table 22-66.
Figure 22-91. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h]
31 1 0
Reserved EV_FIFO_RESET
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-66. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 EV_FIFO_RESET ADC Event Group FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Event Group results memory starting from
the first location.
When this bit is set to 1, the ADC module resets its internal Event Group results memory pointers.
Then this bit automatically gets cleared, so that the ADC module allows the Event Group results
memory to be overwritten only once each time this bit is set to 1. As a result, the EV_FIFO_RESET
bit will always be read as a 0.
The EV_FIFO_RESET bit will only have the desired effect when the Event Group results memory is
in an overrun condition. It must be used when the data already available in the results memory can
be discarded.
If the application needs the Event Group memory to always be overwritten with the latest available
conversion results, then the OVR_EV_RAM_IGN bit in the Event Group operating mode control
register (ADEVMODECR) needs to be set to 1.
22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)
ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) is shown in Figure 22-92 and
described in Table 22-67.
Figure 22-92. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch]
31 1 0
Reserved G1_FIFO_RESET
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-67. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 G1_FIFO_RESET ADC Group1 FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Group1 results memory starting from the
first location.
When this bit is set to 1, the ADC module resets its internal Group1 results memory pointers. Then
this bit automatically gets cleared, so that the ADC module allows the Group1 results memory to be
overwritten only once each time this bit is set to 1. As a result, the G1_FIFO_RESET bit will always
be read as a 0.
The G1_FIFO_RESETbit will only have the desired effect when the Group1 results memory is in an
overrun condition. It must be used when the data already available in the results memory can be
discarded.
If the application needs the Group1 memory to always be overwritten with the latest available
conversion results, then the OVR_G1_RAM_IGN bit in the Group1 operating mode control register
(ADG1MODECR) needs to be set to 1.
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