ESM Control Registers
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SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
This register is dedicated for Group1 Channel[31:0].
Figure 16-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
[offset = 00h]
31 16
IEPSET[31:16]
R/WP-0
15 0
IEPSET[15:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-3. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
Field Descriptions
Bit Field Value Description
31-0 IEPSET Enable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR1 register.
16.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
This register is dedicated for Group1 Channel[31:0].
Figure 16-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
[offset = 04h]
31 16
IEPCLR[31:16]
R/WP-0
15 0
IEPCLR[15:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-4. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
Field Descriptions
Bit Field Value Description
31-0 IEPCLR Disable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the
ESMIEPSR1 register.
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