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CRC Control Registers
659
SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2)
Figure 18-35. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h]
31 0
PSASIG2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-31. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions
Bit Field Description
31-0 PSASIG2 Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register.
18.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2)
Figure 18-36. Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h]
31 0
PSASIG2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-32. Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions
Bit Field Description
31-0 PSASIG2 Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register.
18.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)
Figure 18-37. Channel 2 CRC Value Low Register (CRC_REGL2) [offset = A8h]
31 0
CRC2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-33. Channel 2 CRC Value Low Register (CRC_REGL2) Field Descriptions
Bit Field Description
31-0 CRC2 Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at
CRC2[31:0] register.
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