Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions (continued)
Bit Field Value Description
9 CLKCLR SPICLK data out clear. This bit is only active when the SPICLK pin is configured as a general-
purpose output pin.
0 Read: The current value on SPICLK is 0.
Write: No effect.
1 Read: The current value on SPICLK is 1.
Write: Logic 0 is placed on SPICLK pin, if it is in general-purpose output mode.
8 ENACLR SPIENA data out clear. This bit is only active when the SPIENA pin is configured as a general-
purpose output pin. A value of 1 written to this bit clears the corresponding ENABLEDOUT bit to 0.
0 Read: The current value on SPIENA is 0.
Write: No effect.
1 Read: The current value on SPIENA is 1.
Write: Logic 0 is placed on SPIENA pin, if it is in general-purpose output mode.
7-0 SCSCLR SPICS data out clear. This bit is only active when the SPICS pin is configured as a general-purpose
output pin.
0 Read: The current value on SCSDOUT is 0.
Write: No effect.
1 Read: The current value on SCSDOUT is 1.
Write: Logic 0 is placed on SPICS pin, if it is in general-purpose output mode.
28.3.12 SPI Pin Control Register 6 (SPIPC6)
NOTE: Register bits vary by device
Register bits 31:24 and 23:16 of SPIPC0 to SPIPC9 reflect the number of SIMO/SOMI data
lines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented.
On devices with less than 8 data lines, only a subset of these bits are available.
Unimplemented bits return 0 upon read and are not writable.
Figure 28-43. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch]
31 24 23 16
SOMIPDR SIMOPDR
R/W-0 R/W-0
15 12 11 10 9 8
Reserved SOMIPDR0 SIMOPDR0 CLKPDR ENAPDR
R-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
SCSPDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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