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CRC Control Registers
651
SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.8 CRC Busy Register (CRC_BUSY)
Figure 18-16. CRC Busy Register (CRC_BUSY) [offset = 38h]
31 16
Reserved
R-0
15 9 8 7 1 0
Reserved CH2_BUSY Reserved CH1_BUSY
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 18-12. CRC Busy Register (CRC_BUSY) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reads return 0. Writes have no effect.
8 CH2_BUSY CH2_BUSY. During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of
the block is compressed and remains set until the last data pattern of the block is compressed. The
flag is cleared when the last data pattern of the block is compressed.
7-1 Reserved 0 Reads return 0. Writes have no effect.
0 CH1_BUSY CH1_BUSY. During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of
the block is compressed and remains set until the last data pattern of the block is compressed. The
flag is cleared when the last data pattern of the block is compressed.
18.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)
Figure 18-17. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) [offset = 40h]
31 20 19 16
Reserved CRC_PAT_COUNT1
R-0 R/W-0
15 0
CRC_PAT_COUNT1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-13. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reads return 0. Writes have no effect.
19-0 CRC_PAT_COUNT1 Channel 1 Pattern Counter Preload Register. This register contains the number of data
patterns in one sector to be compressed before a CRC is performed.
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