PLL
www.ti.com
528
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
14.5.2 PLL Output Control
The outputs from the PLL are the output clock, slip signals and VALID.
• RFSLIP -- the RFSLIP signal indicates that the Output CLK is running too fast relative to INTCLK and
sets a RFSLIP status flag in the Global Status Register (GLBSTAT), of the System and Peripheral
Control Registers, if the slip signal is active during normal PLL operation; the RFSLIP flag is masked
off while the PLL is not active and during the PLL’s lock period.
• FBSLIP -- the FBSLIP signal indicates that the Output CLK is running too slow relative to INTCLK and
sets a FBSLIP status flag in the Global Status Register (GLBSTAT), of the System and Peripheral
Control Registers, if the slip signal is active during normal PLL operation; the FBSLIP flag is masked
off while the PLL is not active and during the PLL’s lock period.
• PLL Slip -- Logical-OR of the two PLL slip signals. Typically this signal is used to generate a
consolidated slip signal to the device (for example, error logic or exception generation). Also used to
gate VALID.
NOTE: Clearing Slip Bits
In order to clear any of the slip bits, it is necessary to disable the PLL first.
• VALID -- is driven based upon whether the output clock, PLL CLK, is gated or is not gated. However,
the VALID signal is dependent upon the PLL Slip signals so that VALID cannot be set if either slip
signal is active.
• PLL Clock -- The PLL output clock runs at the programmed frequency. When enabled, it takes some
time to acquire the programmed frequency (see Section 14.5.2.1). Similarly, the disable has some
timing and constraints (see Section 14.5.2.2).
14.5.2.1 PLL Enable
After setting the PLL control registers, the clock source is enabled by clearing the appropriate bit in the
Clock Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear
Register (CSDISCLR) of the System and Peripheral Control Registers. The bit sends a signal to the PLL
that starts the process of enabling the PLL.
1. The PLL checks to make sure that the oscillator is ON. If not, it turns the oscillator ON.
2. The PLL begins a locking process in which the PLL slews from a starting frequency point to the
programmed frequency. During this lock period, the PLL slip signals are typically active, and the PLL
masks off the signals during this phase. The lock phase takes the following length of time:
Parameter Value
Lock T
Lock
= (512 × T
OSCIN
) + (1024 × NR × T
OSCIN
)
Enable clocks after lock T
Enable
= 6 × T
OSCIN
3. After the lock phase is complete (when lock counters expire), the PLL releases the slip signals to the
system.
4. Then after the slip signals are released and a delay to enable the clocks, the clock is released to the
system and the appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register
(CSVSTAT) of the System and Peripheral Control Registers.
To Next Page
Loading...
Need help?
General
