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Flash Control Registers
377
SPNU563A–March 2018
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F021 Level 2 Flash Module Controller (L2FMC)
7.10.26 Reset Configuration Valid Register (RCR_VALID)
This register reflects the validity of the implicit read.
Figure 7-36. Reset Configuration Valid Register (RCR_VALID) (offset = B4h)
31 16
Reserved
R-0
15 2 1 0
Reserved JSM_VALID RCR_VALID
R-0 R-1 R-1
LEGEND: R = Read only; -n = value after reset
Table 7-38. Reset Configuration Valid Register (RCR_VALID) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 JSM_VALID When the L2FMC finishes the implicit read, it sets this bit to indicate that the contents of
RCR_VALUE0 and RCR_VALUE1 are valid. This bit will be cleared in case there was a double-bit
error during implicit reads.
0 The implicit read has failed. The device level settings may not be correct.
1 Implicit read is successful. Device level settings are correct.
0 RCR_VALID When the L2FMC finishes the implicit read, it sets this bit to indicate that the contents of
RCR_VALUE0 and RCR_VALUE1 are valid. This bit will be cleared in case there was a double-bit
error during implicit reads.
0 The implicit read has failed. The device level settings may not be correct.
1 Implicit read is successful. Device level settings are correct.
7.10.27 Crossbar Access Time Threshold Register (ACC_THRESHOLD)
Figure 7-37. Crossbar Access Time Threshold Register (ACC_THRESHOLD) (offset = B8h)
31 16
Reserved
R-0
15 12 11 0
Reserved ACC_THRESH_CNT
R-0 R/WP-5FFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 7-39. Crossbar Access Time Threshold Register (ACC_THRESHOLD) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Reserved
11-0 ACC_THRESH_CNT 5FFh Configures maximum number of clocks beyond which the L2FMC internal switch will timeout the
access. This can occur due to soft error in internal logic. It is NOT recommended to modify this
register unless a crossbar diagnostic is being performed.
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