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Application Self-Test Flow
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.4.3 Entering CPU Idle Mode
After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken
to idle mode by executing the CPU Idle Instruction asm(“ WFI”).
10.4.4 Entering nHET Idle Mode
After enabling the STC test by writing the STC enable key, the test is triggered only after the nHET
module is put in reset state by writing to bit 0 the HETGCR Global Configuration Register in the nHET
module.
10.4.5 Self-Test Completion and Error Generation
At the end of each interval, the 128 bit MISR value (reflected in registers CPUx_CURMISR[3:0]) from the
DBIST controller is shifted into the STC. This is compared with the golden MISR value stored in the ROM.
At the end of a CPU self-test, the STC controller updates the status flags in the Global Status Register
(STCGSTAT) and resets the CPU. In case of a MISR mismatch or a test timeout, an error is generated
through the ESM module. TEST_ERR signal is asserted when an MISR miscompare occurs during the
self-test. A TO_ERR is asserted when a timeout occurs during the self-test, meaning the test could not
complete within the time specified in the timeout counter preload register STCTPR. However, at the
device level, these two errors are combined and mapped to a single ESM channel. To identify which error
occurred, user software must check the global status register (STCGSTAT) and fail status register
STCFSTAT in the ESM interrupt service routine.
Figure 10-7 illustrates the self-test hardware execution flow chart, based on the assumption that the
device has gone through startup, necessary clocks initialized and SYSESR register bits cleared.
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