Texas Instruments TMS570LC4357 User Manual

VIM Control Registers www.ti.com
692
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Vectored Interrupt Manager (VIM) Module
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)
The interrupt vector register gives the address of the enabled and active IRQ interrupt. Figure 19-43 and
Table 19-20 describe these registers.
Figure 19-43. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h]
31 0
IRQVECREG
R-0
LEGEND: R = Read only; -n = value after reset
Table 19-20. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions
Bit Field Value Description
31-0 IRQVECREG From
Section 19.5
IRQ interrupt vector register. This vector gives the address of the ISR with the highest
pending IRQ request. The CPU reads the address and branches to this location.
19.9.16 FIQ Interrupt Vector Register (FIQVECREG)
The interrupt vector register gives the address of the enabled and active FIQ interrupt. Figure 19-44 and
Table 19-21 describe these registers.
Figure 19-44. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h]
31 0
FIQVECREG
R-0
LEGEND: R = Read only; -n = value after reset
Table 19-21. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions
Bit Field Value Description
31-0 FIQVECREG From
Section 19.5
FIQ interrupt vector register. This vector gives the address of the ISR with the highest
pending FIQ request. The CPU reads the address and branches to this location.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English