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ADC Registers
941
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) is shown in Figure 22-87
and described in Table 22-62.
Figure 22-87. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
[offset = 158h]
31 3 2 0
Reserved MAG_INT_ENA_SET
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-62. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reads return 0. Writes have no effect.
2-0 MAG_INT_ENA_SET Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
0 The enable status of the corresponding magnitude compare interrupt is left unchanged.
1 The corresponding magnitude compare interrupt is enabled.
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) is shown in Figure 22-88
and described in Table 22-63.
Figure 22-88. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
[offset = 15Ch]
31 3 2 0
Reserved MAG_INT_ENA_CLR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-63. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reads return 0. Writes have no effect.
2-0 MAG_INT_ENA_CLR Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
0 The enable status of the corresponding magnitude compare interrupt is left unchanged.
1 The corresponding magnitude compare interrupt is disabled.
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