CPU1
CPU2
POLARITYINVERT
XOR
ESM
N N-8 N
8
Module Operation
www.ti.com
504
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
CPU Compare Module for Cortex-R5F (CCM-R5F)
13.2.2 CPU Input Inversion Diagnostic
There is another way to intentionally create a mismatch between the two CPUs' outputs as a diagnostic
test to self-test the CCM-R5F's CPU Output Compare Diagnostic block. Before the CPU1's outputs are
taken to the CCM-R5F, eight of the output signals are first exclusive-ORed bitwise with the 8-bit
POLARITYINVERT register. After reset, the default value of the POLARITYINVERT register is all zeros.
The resultant values of the 8 signals after the XOR logic with the POLARITYINVERT register will still be
the same as the original 8 signal values. However, by programming the POLARITYINVERT to a non-zero
values it will have the effect to invert the signal values. This intentional inversion on the inputs to the CCM-
R5F will cause the CPU Output Compare Diagnostic to detect a compare error. See Figure 13-2 for
illustration.
Figure 13-2. CPU Input Inversion Scheme
Table 13-4. CPU1 (Main CPU) Signals Being Inverted Before Being Compared
Signals Remark
AWVALIDM Indicates write address and control are valid
ARVALIDM Indicates write address and control are valid
AWVALIDP Indicates write address and control are valid
ARVALIDP Indicates write address and control are valid
HTRANSP[1:0] Indicates write address and control are valid
To Next Page
Loading...
Need help?
General
