EMIF Registers
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SPNU563A–March 2018
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External Memory Interface (EMIF)
21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR)
The SDRAM self refresh exit timing register (SDSRETR) is used to program the amount of time between
when the SDRAM exits Self-Refresh mode and when the EMIF issues another command. The SDSRETR
is shown in Figure 21-21 and described in Table 21-31.
Figure 21-21. SDRAM Self Refresh Exit Timing Register (SDSRETR) [offset = 3Ch]
31 16
Reserved
R-0
15 5 4 0
Reserved T_XS
R-0 R/W-9h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-31. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved. The reserved bit location is always read as 0.
4-0 T_XS 0-1Fh This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command,
minus one.
T_XS = Txsr / t
EMIF_CLK
- 1
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