Texas Instruments TMS570LC4357 User Manual

SCM Registers www.ti.com
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SPNU563A–March 2018
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SCR Control Module (SCM)
3.4.6 SCM Initiator Active Status Register (SCMIASTAT)
Figure 3-10. SCM Initiator Active Status Register (SCMIASTAT) [offset = 18h]
31 16
Reserved
R-0
15 14 13 12 11 10 9 8
Reserved IAST13 IAST12 IAST11 IAST10 IAST9 IAST8
R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
IAST7 IAST6 IAST5 IAST4 IAST3 IAST2 IAST1 IAST0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after synchronous reset by system reset
Table 3-7. SCM Initiator Active Status Register (SCMIASTAT) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved. Read returns 0.
13-0 IASTn IA (Initiator Agent) Status. Each bit n indicates that there is a pending transaction on the corresponding
IAn. Refer to Interconnect chapter of the TRM for mapping of master port to the SCMIASTAT register
bit.
0 No pending transaction in IAn.
1 Pending transaction in IAn.
3.4.7 SCM Target Active Status Register (SCMTASTAT)
Figure 3-11. SCM Target Active Status Register (SCMTASTAT) [offset = 20h]
31 16
Reserved
R-0
15 14 13 12 11 10 9 8
Reserved TAST13 TAST12 TAST11 TAST10 TAST9 TAST8
R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
TAST7 TAST6 TAST5 TAST4 TAST3 TAST2 TAST1 TAST0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after synchronous reset by system reset
Table 3-8. SCM Target Active Status Register (SCMTASTAT) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved. Read returns 0.
13-0 TASTn TA (Target Agent) Status. Each bit n indicates that there is a pending transaction on the corresponding
TAn.Refer to Interconnect chapter of the TRM for mapping of slave port to the SCMTASTAT register bit.
0 No pending transaction in TAn.
1 Pending transaction in TAn.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English