Texas Instruments TMS570LC4357

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419
SPNU563A–March 2018
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Programmable Built-In Self-Test (PBIST) Module
9.5.7 Fail Status Count Registers (FSRC0 and FSRC1)
These registers keep count of the number of failures observed during the memory self-test. The PBIST
controller stops executing the memory self-test whenever a failure occurs in any memory instance for any
of the test algorithms. The value in FSRC0 / FSRC1 gets incremented by one whenever a failure occurs
and gets decremented by one when the failure is processed. FSRC0 is for Port 0 and FSRC1 is for Port 1.
Figure 9-9 and Table 9-8 illustrate the FSRC0 register, while Figure 9-10 and Table 9-9 illustrate the
FSRC1 register.
Figure 9-9. Fail Status Count 0 Register (FSRC0) [offset = 0198h]
31 16
Reserved
R-0
15 8 7 0
Reserved FSRC0
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-8. Fail Status Count 0 Register (FSRC0) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 FSRC0 Fail Status Count 0. Indicates the number of failures on port 0.
Figure 9-10. Fail Status Count Register 1 (FSRC1) [offset = 019Ch]
31 16
Reserved
R-0
15 8 7 0
Reserved FSRC1
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-9. Fail Status Count Register 1 (FSRC1) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 FSRC1 Fail Status Count 1. Indicates the number of failures on port 1.