RAM0
Slave
Port
Master
Port
RAM1
ARM
SCR
2
SCR
HTU
N2HET
Peripheral Bus
Main Datapath
Main Datapath
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Module Operation
1133
SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.2 Module Operation
The HTU is tightly coupled to the N2HET and is not intended to transfer data from other peripheral
modules. It initiates transfers with the help of requests generated by the N2HET program and configurable
control packets. Figure 24-1 shows a system block diagram of the HTU and the main path for the data
transfer. The tight coupling and the dedicated bus into the SCR (Switched Central Resource) reduces the
amount of data transferred on the peripheral bus, which increases the overall system performance.
However if the application decides to use the direct CPU access method to the N2HET RAM, it is free to
do so.
Figure 24-2 shows a more detailed block diagram of the HTU module.
Figure 24-1. System Block Diagram
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