www.ti.com
Overview
697
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
20.1 Overview
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
• Transfer blocks of data between external and internal data memories
• Restructure portions of internal data memory
• Continually service a peripheral
• Page program sections to internal program memory
Since the DMA has two master ports, the selection for the port should be made using the table mentioning
the port to be used for each address region.
20.1.1 Main Features
• CPU independent data transfer
• Two master ports - PortA and PortB (each 64-bits wide) that interface with the Microcontroller's Bus
Matrix System.
• Support for concurrent transfers on up to two different channels
• FIFO buffer (4 entries deep and each 64-bits wide)
• Channel control information is stored in RAM protected by ECC
• Multiple logical channels with individual enable (refer to the data manual for the number of channels on
your device)
• Channel chaining capability
• 48 peripheral DMA requests
• Hardware and Software DMA requests
• 8-, 16-, 32-, or 64-bit transactions supported
• Multiple addressing modes for source/destination (fixed, increment, offset)
• Auto-initiation
• Power-management mode
• Memory Protection for the address range DMA can access with multiple configurable memory regions
(refer datasheet for number of memory regions on your device)
20.1.1.1 Block Diagram
Figure 20-1 gives a top view of the DMA internal architecture. DMA data read and write access happen
through either Port A or B. Both FIFO buffers are each 4 levels deep and 64-bits wide thus allowing a
maximum of 32 bytes to be buffered inside the DMA per channel. DMA requests go into the DMA that can
trigger DMA transfers. Five interrupt request lines go out of the DMA to signal that a certain transfer status
is reached. Register banks hold the memory mapped DMA configuration registers. Local RAM consists of
DMA control packets and is secured by ECC. All the programming / configuration of the DMA controller is
done via the Peripheral bus.
To Next Page
Loading...
Need help?
General
