Texas Instruments TMS570LC4357 User Manual

www.ti.com N2HET Control Registers
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.4.14 XOR Share Control Register (HETXOR)
N2HET1: offset = FFF7 B838h; N2HET2: offset = FFF7 B938h
Figure 23-69. XOR Share Control Register (HETXOR)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8
XOR
SHARE31/30
XOR
SHARE29/28
XOR
SHARE27/26
XOR
SHARE25/24
XOR
SHARE23/22
XOR
SHARE21/20
XOR
SHARE19/18
XOR
SHARE17/16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
XOR
SHARE15/14
XOR
SHARE13/12
XOR
SHARE11/10
XOR
SHARE9/8
XOR
SHARE7/6
XOR
SHARE5/4
XOR
SHARE3/2
XOR
SHARE1/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-30. XOR Share Control Register (HETXOR) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 XORSHARE
n+1 / n
XOR Share Enable
Enable the XOR-share of the same pin for two output HR structures. For example, if bit
XORSHARE1/0 is set, the pin HET[0] will then be commanded by a logical XOR of both HR
structures 0 and 1.
Note: If XOR share bits are used, pins not connected to HR structures (the odd number pin in each
pair) can be accessed as general inputs/outputs.
0 HR Output of HET[n+1] and HET[n] are not XOR shared.
1 HR Output of HET[n+1] and HET[n] are XOR shared onto pin HET[n].

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English