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Flash Control Registers
375
SPNU563A–March 2018
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F021 Level 2 Flash Module Controller (L2FMC)
7.10.24 Raw Address Register (FRAW_ADDR)
Figure 7-34. Raw Address Register (FRAW_ADDR) (offset = 74h)
31 5 4 0
RAW_DATA[31:5] Reserved
R/WP-u R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -u = Unchanged value on internal reset, cleared on power up; -
n = value after reset
Table 7-36. Raw Address Register (FRAW_ADDR) Field Descriptions
Bit Field Description
31-5 RAW_DATA Raw Address.
This register is used during the address tag register test mode, DIAGMODE = 5, to replace the address
bus bits 31:3. The lower 5 bits are not compared during the diagnostic.
4-0 Reserved Reads return 0. Writes have no effect.
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