Filter input
Filter output
Counter
0
Filter input
Filter output
Counter
preload value
0
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N2HET Functional Description
987
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
Figure 23-26. Suppression Filter Counter Operation
Table 23-11. Pulse Length Examples for Suppression Filter
Divider CCDIV VCLK2
Possible values for the suppressed pulse length / frequency resulting from the
programmable 10 bit preload value (0,1,..,1023)
1 100.0 MHz 10 ns, 20 ns, …, 10.22 µs, 10.23 µs 50 MHz, 25 MHz, …, 48.924 kHz, 48.876 kHz
2 50.0 MHz 20 ns, 40 ns, …, 20.44 µs, 20.48 µs 25 MHz, 12.5 MHz, …, 24.462 kHz, 24.414 kHz
3 33.3 MHz 30 ns, 60 ns, …, 30.66 µs, 30.69 µs 16.7 MHz, 8.3 MHz, …, 16.308 kHz, 16.292 kHz
23.2.7 Interrupts and Exceptions
N2HET interrupts can be generated by any instruction that has an interrupt enable bit in its instruction
format. When the interrupt condition in an instruction is true and the interrupt enable bit of that instruction
is set, an interrupt flag is then set in the N2HET Interrupt Flag Register (HETFLG). The address code for
this flag is determined by the five LSBs of the current timer program address. The flag in the N2HET
Interrupt Flag Register (HETFLG) is set even if the corresponding bit in the N2HET Interrupt Enable Set
Register (HETINTENAS) is 0. To generate an interrupt, the corresponding bit in the N2HET Interrupt
Enable Set Register (HETINTENAS) must be 1. In the N2HET interrupt service routine, the main CPU
must first determine which source inside the N2HET created the interrupt request. This operation is
accelerated by the N2HET Offset Index Priority Level 1 Register (HETOFF1) or N2HET Offset Index
Priority Level 2 Register (HETOFF2) that automatically provides the number of the highest priority source
within each priority level. Reading the offset register will automatically clear the corresponding N2HET
interrupt flag that created the request. However, if the offset registers are not used by the N2HET interrupt
service routine, the flag should be cleared explicitly by the CPU once the interrupt has been serviced.
Table 23-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx
Source No. Offset Value
no interrupt 0
Instruction 0, 32, 64... 1
Instruction 1, 33, 65... 2
: :
Instruction 31, 63, 95... 32
Program Overflow 33
APCNT underflow: 34
APCNT overflow 35
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