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Flash Control Registers
373
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
F021 Level 2 Flash Module Controller (L2FMC)
7.10.21 EEPROM Emulation ECC Register (FEMU_ECC)
Figure 7-31. EEPROM Emulation ECC Register (FEMU_ECC) (offset = 60h)
31 16
Reserved
R-0
15 8 7 0
Reserved EMU_ECC
R-0 R/WP-0h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset
Table 7-33. EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 EMU_ECC 0-FFh This register can be written by the CPU in any mode.
This register is used in diagnostic mode 7 to XOR the ECC being delivered to the bus master.
7.10.22 Flash Lock Register (FLOCK)
Figure 7-32. Flash Lock Register (FLOCK) (offset = 64h)
31 16
Reserved
R-0
15 0
ENCOM
R/WP-55AAh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 7-34. Flash Lock Register (FLOCK) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 ENCOM AA55h Enable writes to EE_FEDACCTRL1 register (see Section 7.10.3).
All other values Writes to EE_FEDACCTRL1 are ignored.
It is recommended to leave this register as 55AAh when not writing to the FEDACCTRL1
register.
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