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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.2.15 Memory Protection
The DMA controller is capable of access to the full address range of the device. The protection
mechanism allows the protection of multiple memory regions to restrict accesses to those address ranges.
This will allow the application to protect critical application data from unintentionally being accessed by the
DMA controller.
20.2.15.1 Protection Mechanism
The memory protection mechanism consists of the access privilege for a given memory region, the start
and end address for the region, and notification of an access violation for the protected region.
Each region to be protected is configured by software by writing the start address and end address for
each region into the DMA Memory Protection Registers, DMAMPRxS and DMAMPRxE. The definition of
these registers can be found starting at Section 20.3.1.64. Any region in the valid address space can be
protected from inappropriate accesses.
The access privileges can be set to one of four permission settings as shown below:
• Full access
• Read only access
• Write only access
• No access
The permissions for a given region are selected by writing the appropriate values in the DMA Memory
Protection Control Register (Section 20.3.1.64).
A region of memory not configured for access settings by the registers has "Full Access" privileges.
NOTE: If the regions defined by the start and end addresses overlap, the region defined first in the
register space determines the access privilege. For example, if region 0 and region 1
overlap, the access permissions defined for region 0 will take precedence since region 0
registers are before region 1.
In a case where a memory protection violation occurs, a flag will be set and an interrupt will be generated,
if interrupts are enabled. The DMA Memory Protection Status Register (Section 20.3.1.65) contains the
status flags for the memory protection mechanism, and the DMA Memory Protection Control Register
(Section 20.3.1.64) contains the interrupt enable bits. Upon detection of the memory protection violation,
the DMA Channel that caused the violation will be stopped and the next available DMA channel will be
serviced.
Figure 20-17 Illustrates a protection mechanism.
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