CRC Control Registers
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SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.6 CRC Interrupt Status Register (CRC_STATUS)
Figure 18-14. CRC Interrupt Status Register (CRC_STATUS) [offset = 28h]
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved CH2_TIMEOUT CH2_UNDER CH2_OVER CH2_CRCFAIL CH2_CCIT
R-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0
7 5 4 3 2 1 0
Reserved CH1_TIMEOUT CH1_UNDER CH1_OVER CH1_CRCFAIL CH1_CCIT
R-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0 R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 18-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reads return 0. Writes have no effect.
12 CH2_TIMEOUT Channel 2 CRC Timeout Interrupt Status Flag. This bit is set in both AUTO and Semi-CPU
mode.
User and Privileged mode (read):
0 No timeout interrupt is active.
1 Timeout interrupt is active.
Privileged mode (write):
0 No effect.
1 Bit is cleared.
11 CH2_UNDER Channel 2 CRC Underrun Interrupt Status Flag. This bit is set in AUTO mode only.
User and Privileged mode (read):
0 No Underrun Interrupt is active.
1 Underrun Interrupt is active.
Privileged mode (write):
0 No effect.
1 Bit is cleared.
10 CH2_OVER Channel 2 CRC Overrun Interrupt Status Flag. This bit is set in either AUTO or Semi-CPU
mode.
User and Privileged mode (read):
0 No Overrun Interrupt is active.
1 Overrun Interrupt is active.
Privileged mode (write):
0 No effect.
1 Bit is cleared.
9 CH2_CRCFAIL Channel 2 CRC Compare Fail Interrupt Status Flag. This bit is set in AUTO mode only.
User and Privileged mode (read):
0 No CRC Fail Interrupt is active
1 CRC Fail Interrupt is active
Privileged mode (write):
0 No effect
1 Bit is cleared
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