Texas Instruments TMS570LC4357

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647
SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
Table 18-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions (continued)
Bit Field Value Description
8 CH2_CCITENR Channel 2 Compression Complete Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Compression Complete Interrupt is disabled.
1 Compression Complete Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Compression Complete Interrupt is disabled.
7-5 Reserved 0 Reads return 0. Writes have no effect.
4 CH1_TIMEOUTENR Channel 1 Timeout Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Timeout Interrupt is disabled.
1 Timeout Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Timeout Interrupt is disabled.
3 CH1_UNDERENR Channel 1 Underrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Underrun Interrupt is disabled.
1 Underrun Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Underrun Interrupt is disabled.
2 CH1_OVERENR Channel 1 Overrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Overrun Interrupt is disabled.
1 Overrun Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Overrun Interrupt is disabled.
1 CH1_CRCFAILENR Channel 1 CRC Compare Fail Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 CRC Fail Interrupt is disabled.
1 CRC Fail Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 CRC Fail Interrupt is disabled.
0 CH1_CCITENR Channel 1 Compression Complete Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Compression Complete Interrupt is disabled.
1 Compression Complete Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Compression Complete Interrupt is disabled.