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ESM Control Registers
565
SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4 ESM Control Registers
Table 16-2 lists the ESM registers. Each register begins on a 32-bit word boundary. The registers support
8-, 16-, and 32-bit accesses. The base address for the control registers is FFFF F500h.
Table 16-2. ESM Control Registers
Offset Acronym Register Description Section
00h ESMEEPAPR1 ESM Enable ERROR Pin Action/Response Register 1 Section 16.4.1
04h ESMDEPAPR1 ESM Disable ERROR Pin Action/Response Register 1 Section 16.4.2
08h ESMIESR1 ESM Interrupt Enable Set/Status Register 1 Section 16.4.3
0Ch ESMIECR1 ESM Interrupt Enable Clear/Status Register 1 Section 16.4.4
10h ESMILSR1 Interrupt Level Set/Status Register 1 Section 16.4.5
14h ESMILCR1 Interrupt Level Clear/Status Register 1 Section 16.4.6
18h ESMSR1 ESM Status Register 1 Section 16.4.7
1Ch ESMSR2 ESM Status Register 2 Section 16.4.8
20h ESMSR3 ESM Status Register 3 Section 16.4.9
24h ESMEPSR ESM ERROR Pin Status Register Section 16.4.10
28h ESMIOFFHR ESM Interrupt Offset High Register Section 16.4.11
2Ch ESMIOFFLR ESM Interrupt Offset Low Register Section 16.4.12
30h ESMLTCR ESM Low-Time Counter Register Section 16.4.13
34h ESMLTCPR ESM Low-Time Counter Preload Register Section 16.4.14
38h ESMEKR ESM Error Key Register Section 16.4.15
3Ch ESMSSR2 ESM Status Shadow Register 2 Section 16.4.16
40h ESMIEPSR4 ESM Influence ERROR Pin Set/Status Register 4 Section 16.4.17
44h ESMIEPCR4 ESM Influence ERROR Pin Clear/Status Register 4 Section 16.4.18
48h ESMIESR4 ESM Interrupt Enable Set/Status Register 4 Section 16.4.19
4Ch ESMIECR4 ESM Interrupt Enable Clear/Status Register 4 Section 16.4.20
50h ESMILSR4 Interrupt Level Set/Status Register 4 Section 16.4.21
54h ESMILCR4 Interrupt Level Clear/Status Register 4 Section 16.4.22
58h ESMSR4 ESM Status Register 4 Section 16.4.23
80h ESMIEPSR7 ESM Influence ERROR Pin Set/Status Register 7 Section 16.4.24
84h ESMIEPCR7 ESM Influence ERROR Pin Clear/Status Register 7 Section 16.4.25
88h ESMIESR7 ESM Interrupt Enable Set/Status Register 7 Section 16.4.26
8Ch ESMIECR7 ESM Interrupt Enable Clear/Status Register 7 Section 16.4.27
90h ESMILSR7 Interrupt Level Set/Status Register 7 Section 16.4.28
94h ESMILCR7 Interrupt Level Clear/Status Register 7 Section 16.4.29
98h ESMSR7 ESM Status Register 7 Section 16.4.30
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