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DCC Control Registers
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SPNU563A–March 2018
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Dual-Clock Comparator (DCC) Module
15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Figure 15-15 and Table 15-10 describe the DCC Counter0 Clock Source Selection register.
Figure 15-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 28h]
31 16
Reserved
R-0
15 4 3 0
Reserved CNT0 CLKSRC
R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 CNT0 CLKSRC Clock source for counter0 .
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter0.
Refer to the device datasheet for available clock source options for counter0.
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