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FlexRay Module Registers
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SPNU563A–March 2018
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FlexRay Module
26.3 FlexRay Module Registers
26.3.1 Transfer Unit Registers
Table 26-18 provides a summary of the registers. All registers are organized as 32-bit registers. 8-, 16-,
and 32-bit accesses are supported. For FlexRayTU transfers only, 4 × 32-bit data packages are
supported. The base address for the Transfer Unit registers is FFF7 A000h.
The Transfer Unit State Machine registers use the offset address range 00h to 1FCh.
Transfer Configuration RAM uses the offset address range 00h to 1FCh in normal mode and 00h to 3FCh
in ECC test mode.
Table 26-18. Transfer Unit Registers
Offset Address Acronym Register Description Section
000h GSN0 Global Static Number 0 Section 26.3.1.1
004h GSN1 Global Static Number 1 Section 26.3.1.2
010h GCS Global Control Set Section 26.3.1.3
014h GCR Global Control Reset Section 26.3.1.3
018h TSCB Transfer Status Current Buffer Section 26.3.1.4
01Ch LTBCC Last Transferred Buffer to Communication Controller Section 26.3.1.5
020h LTBSM Last Transferred Buffer to System Memory Section 26.3.1.6
024h TBA Transfer Base Address Section 26.3.1.7
028h NTBA Next Transfer Base Address Section 26.3.1.8
02Ch BAMS Base Address of Mirrored Status Section 26.3.1.9
030h SAMP Start Address of Memory Protection Section 26.3.1.10
034h EAMP End Address of Memory Protection Section 26.3.1.11
040h TSMO1 Transfer to System Memory Occurred 1 Section 26.3.1.12
044h TSMO2 Transfer to System Memory Occurred 2 Section 26.3.1.12
048h TSMO3 Transfer to System Memory Occurred 3 Section 26.3.1.12
04Ch TSMO4 Transfer to System Memory Occurred 4 Section 26.3.1.12
050h TCCO1 Transfer to Communication Controller Occurred 1 Section 26.3.1.13
054h TCCO2 Transfer to Communication Controller Occurred 2 Section 26.3.1.13
058h TCCO3 Transfer to Communication Controller Occurred 3 Section 26.3.1.13
05Ch TCCO4 Transfer to Communication Controller Occurred 4 Section 26.3.1.13
060h TOOFF Transfer Occurred Offset Section 26.3.1.14
06Ch TSBESTAT TCR ECC Single-Bit Error Status Section 26.3.1.15
070h PEADR ECC Error Address Section 26.3.1.16
074h TEIF Transfer Error Interrupt Section 26.3.1.17
078h TEIRES Transfer Error Interrupt Enable Set Section 26.3.1.18
07Ch TEIRER Transfer Error Interrupt Enable Reset Section 26.3.1.18
080h TTSMS1 Trigger Transfer to System Memory Set 1 Section 26.3.1.19
084h TTSMR1 Trigger Transfer to System Memory Reset 1 Section 26.3.1.19
088h TTSMS2 Trigger Transfer to System Memory Set 2 Section 26.3.1.19
08Ch TTSMR2 Trigger Transfer to System Memory Reset 2 Section 26.3.1.19
090h TTSMS3 Trigger Transfer to System Memory Set 3 Section 26.3.1.19
094h TTSMR3 Trigger Transfer to System Memory Reset 3 Section 26.3.1.19
098h TTSMS4 Trigger Transfer to System Memory Set 4 Section 26.3.1.19
09Ch TTSMR4 Trigger Transfer to System Memory Reset 4 Section 26.3.1.19
0A0h TTCCS1 Trigger Transfer to Communication Controller Set 1 Section 26.3.1.20
0A4h TTCCR1 Trigger Transfer to Communication Controller Reset 1 Section 26.3.1.20
0A8h TTCCS2 Trigger Transfer to Communication Controller Set 2 Section 26.3.1.20
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