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FlexRay Module Registers
1295
SPNU563A–March 2018
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FlexRay Module
26.3.1.17 Transfer Error Interrupt Flag (TEIF)
The Transfer Error Interrupt Flag register includes the Transfer Unit error flags. The bits in the TEIF are
cleared by writing a 1.
NOTE: Memory Protection Violation (MPV) and ECC Error (PE) interrupts are nonmaskable and can
not be disabled. Therefore, the MPV and PE bits are not part of the Transfer Error Interrupt
Enable Set/Reset (TEIRES/R) registers.
Figure 26-55. Transfer Error Interrupt Flag (TEIF) [offset_TU = 74h]
31 18 17 16
Reserved MPV PE
R-0 R/W1C-0 R/W1C-0
15 11 10 8 7 6 4 3 2 1 0
Reserved RSTAT RSVD WSTAT Reserved TNR FAC
R-0 R/W1C-0 R-0 R/W1C-0 R-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 26-35. Transfer Error Interrupt Flag (TEIF) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reads return 0. Writes have no effect.
17 MPV Memory Protection Violation.
0 No MPV occurred.
1 MPV occurred.
16 PE ECC Error. The flag signals an ECC multi-bit error to the host. The flag is set when an ECC multi-
bit error in TCR is detected.
Note: ECC single-bit errors in TCR are indicated by a separate SE bit in TCR Single-Bit Error
Status (TSBESTAT).
0 No ECC multi-bit error occurred.
1 ECC multi-bit error occurred.
15-11 Reserved 0 Reads return 0. Writes have no effect.
10-8 RSTAT Status of VBUS on read transfers.
0 Success
1h Addressing error
2h Protection error
3h Timeout error
4h Data error
5h Unsupported addressing mode error
6h Reserved
7h Exclusive read failure
Note: Any value other than 000 indicates a VBUS read error. The information of the specific VBUS
fault is for debug reasons only and is not relevant for normal usage.
7 Reserved 0 Reads return 0. Writes have no effect.
6-4 WSTAT Status of VBUS on write transfers.
0 Success
1h Addressing error
2h Protection error
3h Timeout error
4h Reserved
5h Unsupported addressing mode error
6h Reserved
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