FlexRay Module Registers
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SPNU563A–March 2018
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FlexRay Module
26.3.1.16 ECC Error Address (PEADR)
After an ECC multi-bit error in the Transfer Configuration RAM occurred, the affected address is stored in
this not resettable register.
The contents of the ECC Error Address register as well as the PE bit in the Transfer Error Interrupt Flag
(TEIF) register is cleared automatically when reading the ECC Error Address register.
NOTE: An ECC multi-bit error can only be indicated by the PE bit of TEIF register when PEADR is
cleared. Since the contents of PEADR is undefined after reset, it is recommended to clear
the register by reading it.
Figure 26-54. ECC Error Address (PEADR) [offset_TU = 70h]
31 9 8 0
Reserved ADR
R-0 RC-U
LEGEND: R = Read only; RC = Clear on read; U = value is undefined; -n = value after reset
Table 26-34. ECC Error Address (PEADR) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reads return 0. Writes have no effect.
8-0 ADR 0-1FFh Address of failing TCR location. ADR[8-2] is the TCR word address where the ECC multi-bit error
occurred. ADR[1-0] are always driven as 11.
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