www.ti.com
HTU Control Registers
1155
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)
Figure 24-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h]
31 17 16
Reserved BERINTENA
R-0 R/WP-0
15 9 8 7 1 0
Reserved CORL Reserved RLINTENA
R-0 R/WP-0 R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 24-20. Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reads return 0. Writes have no effect.
16 BERINTENA Bus Error Interrupt Enable Bit
0 The bus error interrupt is disabled for all DCPs.
1 The bus error interrupt is enabled for all DCPs.
15-9 Reserved 0 Reads return 0. Writes have no effect.
8 CORL Continue On Request Lost Error
0 Stop current frame on request lost detection. Please see Section 24.2.3.
1 If CORL is 1 and DCP x is enabled, then DCP x will stay enabled after a request lost condition on DCP
x and element transfers will continue.
7-1 Reserved 0 Reads return 0. Writes have no effect.
0 RLINTENA Request Lost Interrupt Enable Bit
0 The request lost interrupt is disabled for all DCPs. Disabling RLINTENA will not clear the flags in the
RLOSTFL register.
1 The request lost interrupt is enabled for all DCPs. If bits are set in the RLOSTFL flag register at the time
RLINTENA is (re-) enabled, then the according interrupt(s) will occur (in the order of the priority of the
request lines).
To Next Page
Loading...
Need help?
General
